# Principal Physical Design Engineer at Astera Labs

- Company: Astera Labs
- Status: Open
- Workplace: On-site
- Location: Singapore, Singapore
- Level: Principal
- Discipline: Backend
- Employment: Full-time
- Posted: 2026-10-13
- Skills: CXL, Ethernet, NVLink, PCIe, UALink
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4738758005

## Description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . 
 About the Role 
 We are seeking a Senior Physical Design Engineer to join our high-performance design team working on next-generation transceiver IPs targeting the TSMC 3nm and advanced technology nodes 
 Key Responsibilities 
• 
 Perform block-level and top-level physical implementation including floorplanning, placement, clock tree synthesis (CTS), routing, and physical verification for high-speed designs in advanced technology nodes.
• 
 Collaborate with RTL and STA teams to ensure clean handoffs and support timing, area, and power convergence.
• 
 Apply advanced physical design techniques to support multiple voltage and frequency domains, hierarchical design, and physical-aware synthesis.
• 
 Work on key physical design areas including:
• 
 EM/IR analysis and power grid optimization
• 
 Congestion analy

More Astera Labs roles: https://deviantjobs.com/companies/astera-labs