Scaling · Hardware
About the Team
OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform.
About the Role
We are seeking a highly skilled Physical Design Engineer with deep expertise in physical design and methodology. This individual contributor role sits within our physical design team and is central to delivering power, performance, and area (PPA) optimized datapath and interconnect solutions for next-generation AI accelerators.
You’ll work closely with RTL designers to define and execute on physical design strategies. You will develop tools, flows and methodologies to increase team productivity. Your work will directly impact silicon’s performance and cost efficiency, as well as the team’s execution velocity and quality.
In this role, you will
- Develop, build and own tools, flows and methodologies for physical implementation
- Own physical implementation of floorplan blocks from floorplanning to final signoff
- Collaborate with RTL designers to drive optimal block implementation solutions
- Analyze and optimize design for timing, power, and area trade-offs, working in collaboration with EDA vendors and ASIC partners
Qualifications
- BS w/ 4+ or MS wit