CXL · Ethernet · NVLink · PCIe · UALink
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com .
Principal SerDes Bring-up Validation Engineer
Role Overview
Astera Labs is seeking a Principal SerDes Bring-up Validation Engineer to join a cutting-edge mixed-signal design team and lead end-to-end post-silicon bring-up, validation, and characterization. You will own bring-up and characterization strategies from the ground up, translating design and product requirements into measurable test objectives, pass/fail criteria, and schedules, and driving hands-on lab work to verify silicon against specification and performance targets.
As a hyper-growth company building the purpose-built connectivity that powers rack-scale AI infrastructure, the speed and rigor of our silicon validation directly shape what we can ship. You will partner closely with AMS design, firmware, and system teams to build automated te